`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: WuHan University
// Engineer: Leequo94
// 
// Create Date: 2018/09/13 
// Design Name: 
// Module Name: max_filer_custom
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// input sequence: 
// 例化的三个参数分别为 卷积核大小\行\列数
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module max_filer_custom # 
( 
    parameter   KERNERL_SIZE = 39,
    parameter   COL = 1920,
    parameter   ROW = 1080
)
(
    input       wire            clk,
    input       wire            rst_n,
    input       wire            s_axis_tvald,
    input       wire    [7:0]   s_axis_tdata,
    output      wire            m_axis_tvald,
    output      wire    [7:0]   m_axis_tdata
);
wire [7:0] m_axis_max_filter2x2_tdata;
max_filter2x2 # 
( 
    .COL ( COL ),
    .ROW ( ROW )
) max_filter2x2_inst 
(
    .clk             ( clk                        ), // input       wire            
    .rst_n           ( rst_n                      ), // input       wire            
    .s_axis_tvald    ( s_axis_tvald               ), // input       wire            
    .s_axis_tdata    ( s_axis_tdata               ), // input       wire    [7:0]   
    .m_axis_tvald    ( m_axis_max_filter2x2_tvald ), // output      wire            
    .m_axis_tdata    ( m_axis_max_filter2x2_tdata )  // output      wire    [7:0]   
);

wire [KERNERL_SIZE-2:0] data_vld;
wire [(KERNERL_SIZE-1)*8-1:0] data;
assign data_vld[0] = m_axis_max_filter2x2_tvald;
assign data[7:0] = m_axis_max_filter2x2_tdata;

generate 
genvar i;
    for (i = 1;i < KERNERL_SIZE-1;i = i+1)
    begin : max_filter2x2_loop
        max_filter2x2 # 
        ( 
            .COL ( COL - i ),
            .ROW ( ROW - i )
        ) max_filter2x2_inst0 
        (
            .clk             ( clk                   ), // input       wire            
            .rst_n           ( rst_n                 ), // input       wire            
            .s_axis_tvald    ( data_vld[i-1]         ), // input       wire            
            .s_axis_tdata    ( data[i*8-1:(i-1)*8]   ), // input       wire    [7:0]   
            .m_axis_tvald    ( data_vld[i]           ), // output      wire            
            .m_axis_tdata    ( data[(i+1)*8-1:i*8]   )  // output      wire    [7:0]   
        );
    end 
endgenerate 


assign m_axis_tvald = data_vld[KERNERL_SIZE-2];
assign m_axis_tdata = data[(KERNERL_SIZE-1)*8-1:(KERNERL_SIZE-2)*8];

endmodule 
